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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners 6-channel integrated lcd supply ISL98604 the ISL98604 is a high power, fully programmable 6-channel output control ic targeted at large panel lcd displays. the ISL98604 integrates a high power, boost converter and delay switch for avdd generation, one vio asynchronous buck regulator, two synchronous buck regulators for havdd and vcore supply generation, and linear regulator controllers for v on and v off charge pumps. operating at 750khz, the avdd b oost converter features a 4.0a boost fet and 6-bit resolution programmable from 12.7v to 19.0v. the delay switch is also integrated for power sequence. the asynchronous buck converter for vio supply features an integrated 2a fet. it also operates at 750khz internal clock and compensation features. the two synchronous bucks are integrated with controller, upper, and lower side switches for havdd and vcore generation with internal compensation. the havdd and vcore outputs are both programmable ranging from 6.4v to 9.55v and 0.9v to 2.4v, respectively. dual linear regulator controllers are provided to allow generation of accurate v on and v off voltages in conjun ction with external charge pumps and bipolar power transistors. v on output voltage can be compensated adoptively by temperature sensing. all output voltages are programm ed through iic and stored in eeprom. alternative factory set voltages are available for ISL98604; please contact consumer product marketing via email at consumer-all@intersil.com . features ? 8v to 16.5v input supply ? avdd boost up to 19.0v, with integrated 4.0a peak fet ? havdd synchronous buck for 8v with 1a peak fet ? overvoltage protection (ovp) ? internal avdd delay fet ? dual linear regulator controllers for v on and v off ?v on temperature compensation ?vio buck with integrated 2a peak fet ? vcore synchronous buck with integrated 1a peak fet ? internal feedback and compensation ? programmable output control with iic ? programmable sequencing with iic ? uvlo and otp protection ? thermally enhanced 5x5 thin qfn package ? pb-free (rohs compliant) applications ?lcd tv pin configuration ISL98604 (40 ld 5x5 tqfn) top view a0 1 2 4 12 11 10 9 8 7 6 5 3 13 14 31 30 20 21 22 23 24 25 26 27 29 28 15 16 17 18 19 38 37 36 35 34 33 32 pg scl vdc swb1 pvin1 nc swb2 nc thermal pad pvin2 agnd pvin3 phase2 vcore drvn sda avin en nc 40 39 nc nc nc swo vio nc pgnd1 pgnd2 sw1 sw2 tcomp fbn fbp drvp swin phase1 havdd pgnd3 ss comp pgnd4 december 17, 2012 fn7687.0
ISL98604 2 fn7687.0 december 17, 2012 typical application circuit vin: 12v 8v~16.5v c1 10f c4 10f c04 10f c02 20f c03 20f 4.7h l1 ss34 d1 lx avdd: 16v 12.7v~19.0v vio: 3.3v 3.0v~3.7v c11 20f l2 6.8h d11 ss33 r01 5.6k c01 15nf c05 47nf c63 1f r63 700 c65 10f r61 10k r62 10k avdd bat54s d61 0 r64 c64 0.1f von: ht: 26v 7v~32v lt: 28v, 19v~34v vcore: 1.8v, 0.9v~2.4v c21 10f l3 2.2f fmmt3906 q1 tdk ntc 1068 e type 10k swb1 mmbt3904 q2 r53 0 c53 0.22f r54 700 c52 100nf voff: 5v, -8.1v~1.8v c51 4.7f d51 d52 bat54s vdc async mode async mode pc havdd: 8.0v 6.4v~9.55v vio vio vio r42 10k r44 100k r43 100k vin c31 4.7f l4 6.8h pgood c3 10f c40 1f c2 10f vin pvin1 pvin2 swb1 swb2 vio sw1 sw2 swin swo comp pgnd1 pgnd2 ss vcore phase2 pgnd4 drvp fbp tcomp pvin3 havdd phase1 pgnd3 drvn fbn scl sda a0 en pg avin vdc agnd vio buck boost vcore buck von c.p. havdd buck voff c.p. interface/sequence ntc lx
ISL98604 3 fn7687.0 december 17, 2012 block diagram pvin2 pvin1 s r q slope compensation ref comp s r q sw1 sw2 pgnd1 pgnd2 swb1 i 2 c interface and sequence control ss scl vio fosc 750khz fosc 750khz agnd eeprom sca a0 von linear regulator control voff linear regulator control tcomp fbp fbn drvn 4.5v regulator vdc pgood monitoring pg swo s r q pgnd3 fosc 1mhz ref q phase1 avin swin swb2 s r q pgnd4 fosc 3mhz vcore ref q phase2 avin vio havdd delay fet swo drvp en avin pvin3 ref
ISL98604 4 fn7687.0 december 17, 2012 pin descriptions pin # symbol description 1 en ic enable pin; pull high to enable all the outputs. 2 tcomp temperature compensation input, connect ntc resistor in the resistor ladder from vdc to gnd to set the curve of v on vs temperature. 3 vdc internal linear regulator output, connecte d to external 1f capacitor close to the pin. 4 agnd analog ground pin. 5 avin internal regulator supply pin; connect to external 10f capacitor close to the pin. 6 pvin3 havdd buck power input pin; connect to external 10f capacitor close to the pin. 7, 19, 23, 25, 34, 37, 40 nc not connected. 8 phase1 havdd buck switch node; connect an inductor to the pin for synchronous mode, or connect a inductor and a schottky diode to the pin for asynchronous mode. 9 havdd havdd buck output feedback input pin. 10 pgnd3 havdd buck power ground. 11 ss avdd boost and havdd buck soft-start timing capacitor connection for step-up. 12 comp avdd boost compensation pin; connect a 5.6k resistor and 15nf capacitor in series to the pin. 13, 14 pgnd2, 1 avdd boost power ground. 15, 16 sw2, 1 avdd boost switch node connection. 17 swin avdd delay fet input, connect a 10f capacitor close to the pin. 18 swo avdd delay fet output, connect a 22f capacitors close to the pin. 20 drvp positive charge pump ldo transistor driver, conn ect the base of an extern al pnp bipolar to the pin. 21 fbp positive charge pump output feedback input pin. 22 fbn negative charge pump output feedback input pin. 24 drvn negative charge pump ldo transistor driver, conn ect the base of an external npn bipolar to the pin. 26 pg power good output. 27 a0 iic slave address select pin. 28 scl iic clock pin. 29 sda iic data pin. 30 vcore vcore buck output feedback input pin. 31 pgnd4 vcore buck power ground. 32 phase2 vcore buck switch node, connect an inductor to the pin for synchronous mode, or connect a inductor and a schottky diode to the pin for asynchronous mode. 33 vio vio buck output feedback input pin. 35, 36 swb1, 2 vio asynchronous buck switch node connection. 38, 39 pvin2, 1 vio buck and vcore buck power input pin; connect to external 10f capacitor close to the pin. -padthermal pad.
ISL98604 5 fn7687.0 december 17, 2012 ordering information (note 1) part number (notes 2, 3, 4) part marking avdd boost (v) havdd buck (v) vio buck (v) vcore buck (v) v on lt (v) v on ht (v) v off (v) dly1 (ms) dly2 (ms) dly3 (ms) temp range (c) package (pb-free) pkg. dwg. # ISL98604irtz isl9860 4irz 16 8.0 3.3 1.0 28 26 -5 10 30 30 -40 to +85 40 ld 5x5 tqfn l40.5x5d ISL98604irtz-evz evaluation board notes: 1. for availability and lead time of devices with voltage and powe r-on timing combinations not listed in the table, please conta ct intersil marketing via email at consumer-all@intersil.com . 2. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. for moisture sensitivity level (msl), please see device information page for ISL98604 . for more information on msl please see techbrief tb363 .
ISL98604 6 fn7687.0 december 17, 2012 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 test circuits and waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 havdd synchronous buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 vio buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 vcore buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v on linear-regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 v off linear-regulator controll er and charge pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 calculation of the linear regulator base-e mitter resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 von/voff charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 von temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 i2c control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ISL98604 7 fn7687.0 december 17, 2012 absolute maximum ratings (t a = +25c) thermal information drvp to agnd and pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +45v fbp to agnd and pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +36v fbn to agnd and pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3v to -10v sw1, sw2, swi, and swo . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +24v pvin1, pvin2, avin, swb1, swb2, phase1, phase2, havdd, and en to agnd and pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +18.6v drvn, vdc, vcore, ss, pgood, scl, sda, and a0 to agnd and pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.5v voltage between agnd and pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v all other pins to gnd, agnd and pgnd . . . . . . . . . . . . . . . . -0.5v to +5.5v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101). . . . . . . . . . . . . 750v latch up (tested per jesd-78b; class ii, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 5x5 tqfn package (notes 5, 6) . . . . . . . . . 32 2.4 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v to 16.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = 12v, en = vdc, avdd = 16v, v on = 28v, v off = -5v, havdd = 8.0v, vio = 3.3v, vcore = 1.0v. boldface limits apply over the operating temperature range, t a = -40c to +85c, unless otherwise noted. symbol parameter test conditions min (note 7) typ max (note 7) units supply pins p vin +sup supply voltage 8 12 16.5 v iv in +sup supply current when disabled en = 0v 1.25 ma iv in +sup supply current when enabled en = vdc, no loading on all channels 8 ma ien enable input bias current en = 0 0.01 0.1 a en = vdc 10 15 a v ldo internal ldo output voltage 4.5 v avdd boost v avdd output voltage range 1.14*vin 16 19.0 v acc avdd output voltage accuracy avdd = 16v, i load = 100ma -2 2 % i swpl_avdd switch peak current limit boost peak current limit 3.5 4 4.5 a eff avdd peak efficiency 93 % i swlk_avdd switch leakage current 22 a r ds(on)_avdd switch on-resistance t a = +25c, i sw = 500ma 0.125 0.19 dv avdd /dv in line regulation 9.5v < pvin < 13.5v, i load = 200ma, 0.08 % dv avdd /di out load regulation 100ma < i load < 500ma 0.5 % d max_avdd maximum duty cycle f osc = 750khz 82 87 % d min_avdd minimum duty cycle f osc = 750khz 12 16 % f osc_avdd oscillator frequency internal osc 675 750 825 khz avdd delay switch r ds(on)_dly switch on-resistance 0.15 0.24
ISL98604 8 fn7687.0 december 17, 2012 i swpl_dly switch peak current limit 2.3 3.1 3.8 a fet timeout delay fet fault timeout i swo > i dly 1ms i swpl_immed switch high current limit, immediate shut down once triggered 6.0 a i swlk_ dly leakage current when disabled v in = 16.5v, v swin = 19v, v swo = 0v, en = 0v 5 20 a havdd sync buck v havdd output voltage range internal feedback 6.4 8 9.55 v acc havdd output voltage accuracy havdd = 8v -1.6 1.6 % i swpl_havdd switching peak current limit 1 a i swrl_havdd lower switch reverse current limit 0.65 0.9 1.15 a eff havdd peak efficiency 93 % r ds(on)_u_havdd upper switch on-resistance t a = +25c , i sw = 500ma 0.3 0.37 r ds(on)_l_havdd lower switch on-resistance t a = +25c , i sw = 500ma 0.3 0.37 i fb_havdd feedback input current 11 a dv havdd /dv in line regulation 9.5v < pv in < 13.5v, i load = 200ma 0.3 % dv havdd /di out load regulation 200ma < i load < 1000ma 0.3 % i swlk_havdd switch leakage current t a = +25c 5 20 a dmax_havdd maximum duty cycle f osc = 750khz 85 90 % d min_havdd minimum duty cycle f osc = 750khz 15 % f osc_havdd oscillator frequency internal osc 675 750 825 khz vio buck v io output voltage range internal feedback 3.0 3.3 3.7 v acc vio output voltage accuracy v io = 3.3v -2.25 2.25 % i vio output current internal feedback 0.7 a i swpl_vio switch peak current limit current limit 2 a eff vio peak efficiency see graphs and ?applications information? on page 15 for component recommendations 86 % r ds(on)_vio switch on-resistance t a = +25c, i sw = 500ma 0.200 0.300 dv vio /dv in line regulation 9.5v < pv in < 13.5v, i load = 200ma 0.3 % dv vio /di out load regulation 200ma < i load < 1000ma 0.3 % i fb_vio feedback input current 2.5 100 na i swlk_vio switch leakage current t a = +25c 5 20 a d max_vio maximum duty cycle f osc = 750khz 85 86 % d min_vio minimum duty cycle f osc = 750khz 10 15.5 % f osc_vio oscillator frequency internal osc 675 750 825 khz vcore buck v core output voltage range internal feedback 0.9 1.0 2.4 v acc vcore output voltage accuracy v core = 1.0v -2.5 2.5 % electrical specifications v in = 12v, en = vdc, avdd = 16v, v on = 28v, v off = -5v, havdd = 8.0v, vio = 3.3v, vcore = 1.0v. boldface limits apply over the operating temperature range, t a = -40c to +85c, unless otherwise noted. (continued) symbol parameter test conditions min (note 7) typ max (note 7) units
ISL98604 9 fn7687.0 december 17, 2012 i core output current 0.5 a i swpl_vcore switch peak current limit current limit 1 a eff vcore peak efficiency see graphs and ?applications information? on page 15 for component recommendations 86 % r ds(on)_u_vcore upper switch on-resistance t a = +25c , i sw = 500ma 0.18 r ds(on)_l_vcore lower switch on-resistance t a = +25c , i sw = 500ma 0.18 dv vcore /dv in line regulation of vcore buck 9.5v < pv in < 13.5v, i load = 200ma 0.1 % dv vcore /di out load regulation of vcore buck 200ma < i load < 500ma 0.3 % i fb_vcore feedback input current v vcore = 1.8v 5 a i swlk_vcore switch leakage current 3 10 a d max_vcore maximum duty cycle f osc = 3mhz 85 90 % d min_vcore minimum duty cycle f osc = 3mhz 8 % f osc_vcore oscillator frequency internal osc 1.32 1.50 1.68 mhz v on ldo v von output voltage range low temperature 19 28 34 v high temperature 17 26 32 v acc von output voltage accuracy v on = 28v -2.1 2.1 % dv on /di out load regulation i drvp = 60a to 120a with mmbt3906 pnp, related resistors are shown in the application circuit 0.64 % dv on /dv in line regulation i drvp = 100a, v in = 9.5v to 14v 0.5 % i drvp positive source current (max) v fbp = 1.15v, v drvn = 10v 3 6ma i leak_drvp drvp off leakage current v fbp = 1.40v, v drvn = 30v 0.1 10 a v tcomp_th (note 2) threshold voltage in temp. compensation 1.265 v v tcomp_hyst hysteresis voltage in temp. compensation v ref = 1.265v 20 mv v off ldo v voff output voltage range -8.1 -5 -1.8 v acc voff output voltage accuracy v off = -5v -3.75 3.75 % i fbn ldo input bias current v fbn = -5v 11 a dv off /di out load regulation i drvn = 60a to 120a with mmbt3904 npn, related resistors are shown in the application circuit, i out = 200ma 2.7 % i drvn negative source current v fbn = 0.6v, v drvn = -10v 3 5ma i leak_drvn drvn off leakage current v fbn = 0.5v, v drvn = -6v 0.1 10 a logic inputs v hi logic ?high? scl, sda, a0 1.85 v en 1.6 v v lo logic ?low? scl, sda, a0 0.85 v en 0.675 v electrical specifications v in = 12v, en = vdc, avdd = 16v, v on = 28v, v off = -5v, havdd = 8.0v, vio = 3.3v, vcore = 1.0v. boldface limits apply over the operating temperature range, t a = -40c to +85c, unless otherwise noted. (continued) symbol parameter test conditions min (note 7) typ max (note 7) units
ISL98604 10 fn7687.0 december 17, 2012 i lg_pd logic pin pull-down current v lg > v lo 25 a i 2 c f scl (note 8) scl frequency 400 khz t in (note 8) pulse width suppression time at sda and scl inputs any pulse narrower than max spec is suppressed 50 ns t aa (note 8) scl falling edge to sda output data valid scl falling edge crossing 30% of vo_ldo, until sda exits the 30% to 70% of vo_ldo window 900 ns t buf (note 8) time the bus must be free before the start of a new transmission sda crossing 70% of vo_ldo during a stop condition, to sda crossing 70% of vo_ldo during the following start condition 1300 ns t low (note 8) clock low time measured at the 30% of vo_ldo crossing 1300 ns t high (note 8) clock high time measured at the 70% of vo_ldo crossing 600 ns t su:sta (note 8) start condition setup time scl rising edge to sda falling edge. both crossing 70% of vo_ldo 600 ns t hd:sta (note 8) start condition hold time sda fal ling edge crossing 30% of vo_ldo to scl falling edge crossing 70% of vo_ldo 600 ns t su:dat (note 8) input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge cross 30% of v cc 100 ns t hd:dat (note 8) input data hold time from sc l falling edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0 900 ns t su:sto (note 8) stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge cross 30% of v cc 600 ns t hd:st0 (note 8) stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v cc 600 ns t dh (note 8) output data hold time from scl falling edge crossing 30% of v cc, until sda enters the 30% to 70% of v cc window 0 ns t r (note 8) sda and scl rise time depend on load 1000 ns t su:a (note 8) nwr condition setup time from nwr rising/falling edge crossing 70/30% of v cc , to sda falling edge cross 30% of v cc (start) 600 ns t hd:a (note 8) nwr data hold time from sd a rising edge crossing 70% of v cc (stop) to nwr rising/falling edge crossing 70/30% of v cc window 800 ns t f (note 8) sda and scl fall time 300 ns cb (note 8) i 2 c bus capacitive load 400 pf c sda (note 8) capacitance on sda 5pf c scl (note 8) capacitance on scl nwr = 0 5 pf nwr = 1 5 pf t wp (note 8) non-volatile write cycle time 12 20 ms eeprom t eeprom eeprom programming time t a = +25c 90 ms r eeprom eeprom memory retention t a = +25c 88 khrs electrical specifications v in = 12v, en = vdc, avdd = 16v, v on = 28v, v off = -5v, havdd = 8.0v, vio = 3.3v, vcore = 1.0v. boldface limits apply over the operating temperature range, t a = -40c to +85c, unless otherwise noted. (continued) symbol parameter test conditions min (note 7) typ max (note 7) units
ISL98604 11 fn7687.0 december 17, 2012 c eeprom eeprom read/write cycles t a = +25c 1 kcyc fault detection threshold ovp overvoltage protection off threshold to shutdown ic 20.5 v v uvlo undervoltage lock out threshold pv in rising 7.2 7.5 7.9 v pv in falling 6.0 6.3 6.6 v t off thermal shutdown all channels temperature rising 140 c start-up and soft-start i ss_avdd soft-start current c ss = 47nf 6 a t ss_havdd boost and havdd buck soft-start time c ss = 47nf 10 ms t ss_von positive charge pump soft-start period 6.4 ms t ss_voff negative charge pump soft-start period t ss_voff = -1.6*v off -15 1.6 9 ms t dly1 delay time from vio to /rst start from 90% of vio 0 10 ms t dly2 delay time from v off to avdd start from 90% of v off 0 30 ms t dly3 delay time from avdd to v on start from 90% of avdd 0 30 ms power good block v pgood pgood output low voltage ipgood = 1ma 0.007 0.025 v i pgleak pgood leakage current vpgood = 3v 0.05 a notes: 7. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. 8. limits established by design or char acterization but not production tested. electrical specifications v in = 12v, en = vdc, avdd = 16v, v on = 28v, v off = -5v, havdd = 8.0v, vio = 3.3v, vcore = 1.0v. boldface limits apply over the operating temperature range, t a = -40c to +85c, unless otherwise noted. (continued) symbol parameter test conditions min (note 7) typ max (note 7) units
ISL98604 12 fn7687.0 december 17, 2012 typical performance curves figure 1. avdd boost efficiency figu re 2. avdd boost load regulation figure 3. avdd boost line regulation figure 4. avdd boost transient response figure 5. havddbuck efficiency figure 6. havdd buck regulation 84 85 86 87 88 89 90 91 92 93 94 95 0 0.2 0.4 0.6 0.8 1.0 1.2 i_avdd (a) efficiency (%) l = rlf7030t-4r7m3r4 d = ss34 v in = 12v -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.1 0.3 0.5 0.7 0.9 1.1 i_avdd (a) load regulation (%) v in = 12v -0.03 -0.02 -0.02 -0.01 -0.01 0.00 0.01 0.01 9 10 11 12 13 14 v in (v) line regulation (%) i avdd = 200ma v in = 12v avdd ripple (500mv/div) i avdd (100ma/div) 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i_havdd (a) efficiency (%) l = rlf7030t-6r8m2r8 v in = 12v -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.2 0.4 0.6 0.8 i_havdd (a) load regulation (%) v in = 12v
ISL98604 13 fn7687.0 december 17, 2012 figure 7. havdd buck line regulation figure 8. havdd buck transient response figure 9. vio buck efficiency figure 10. vio buck load regulation figure 11. vio buck line regulation figure 12. vio buck transient response typical performance curves (continued) -0.10 -0.05 0.00 0.05 0.10 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 v in (v) line regulation (%) i havdd = 200ma havdd ripple (50mv/div) i havdd (100ma/div) 60 65 70 75 80 85 90 0 0.5 1.0 1.5 2.0 i_vio (a) efficiency (%) l = rlf7030t-6r8m2r8 v in = 12v d = ss33 -0.15 -0.10 -0.05 0.00 0.05 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i_vio (a) load regulation (%) v in = 12v 0.00 0.01 0.01 0.02 0.02 0.03 0.03 0.04 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 v in (v) line regulation (%) i vio = 200ma vio ripple (50mv/div) i vio (100ma/div) v in = 12v
ISL98604 14 fn7687.0 december 17, 2012 test circuits and waveforms figure 13. vcore buck efficiency figure 14. vcore buck load regulation figure 15. vcore buck line regulation figure 16. vcore buck transient response figure 17. v on load regulation figure 18. v on line regulation 75 77 79 81 83 85 87 89 91 93 95 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i_vcore (a) efficiency (%) v in = 12v l = rlf7030t-2r2m5r4 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i_vcore (a) v in = 12v load regulation (%) 0.00 0.00 0.00 0.00 0.01 0.01 0.01 0.01 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 v in (v) i vcore = 200ma line regulation (%) vcore ripple (50mv/div) i vcore (100ma/div) v in = 12v -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0 0.01 0.02 0.03 0.04 0.05 i_von (a) load regulation (%) v in = 12v -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 9.5 10.5 11.5 12.5 13.5 v in (v) i von = 20ma line regulation (%)
ISL98604 15 fn7687.0 december 17, 2012 applications information the ISL98604 provides a complete power solution for tft lcd applications. the system consists of one boost converter to generate a vdd voltage for column drivers, one asynchronous buck converter to provide voltage to logic circuit in the lcd panel, two synchronous bucks for core voltage and havdd, ldo controllers for v on and v off charge pump outputs, and a vdd delay fet. with the high output current capability, this part is ideal for lcd tv and monitor panel application. boost converter operation the avdd boost converter is a current mode pwm converter operating at a fixed switching frequency (750khz). it can operate in both discontinuous conduction mode (dcm) at light loads and continuous mode (ccm). in co ntinuous current mode, current flows continuously in the induct or during the entire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. the boost converter uses a summ ing amplifier architecture for voltage feedback, current feedback, and slope compensation. a comparator looks at the peak inductor current cycle-by-cycle and terminates the pwm cycle if the current limit is triggered. since this comparison is cycle based, the pwm output will be released after the peak current goes be low the current limit threshold. the current through the mosfet is limited to 4a peak. this restricts the maximum output current (average) based on equation 2: where di l is peak to peak inductor ripple current, and is set by equation 3. f s is the switching frequency (750khz). ISL98604 uses internal feedback resistor divider to divide the output voltage down to the nominal reference voltage. the boost converter output voltage is programmable through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. input capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converter. a ceramic capacitor with low esr should be chosen to minimize the ripple. the voltage rating of input capacitor should be larger than the maximum input voltage. some capacitors are recommended in table 1. boost inductor the boost inductor is a critical part which influences the output voltage ripple, transient response , and efficiency. the selection of inductor should be based on its maximum current (i sat ) characteristics, power dissipati on (dcr) and size. values of 3.3h to 10h are recommended to match the internal slope compensation as well as to main tain a good transient response performance. the inductor must be able to handle the average and peak currents shown in equations 4 and 5: where eff is the efficiency of the boost converter; 90% can be used in calculation as approximation. figure 19. v off load regulation figure 20. v off line regulation test circuits and waveforms (continued) -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0 0.01 0.02 0.03 0.04 0.05 i_voff (a) load regulation (%) v in = 12v 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 9.5 10.5 11.5 12.5 13.5 v in (v) i voff = 20ma line regulation (%) v boost v in ------------------ 1 1d ? ------------- = (eq. 1) i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- = (eq. 2) table 1. boost converter input capacitor recommendation capacitor size vendor part number 10f/25v 1206 tdk c3216x7r1e106k 22f/25v 1206 murata grm31cr61e226ke15l i l v in l --------- d f s ---- - = (eq. 3) i lavg i o 1d ? () xeff ------------------------------ = (eq. 4) i lpk i lavg i l 2 -------- + = (eq. 5)
ISL98604 16 fn7687.0 december 17, 2012 some inductors are recommended in table 2. rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode must be higher than the maximum output voltage. also the average/peak current rating of the selected schottky diode must meet the outp ut current and peak inductor current requirements. table 3 sh ows some recommendations for boost converter diodes. output capacitor the output capacitors smooths the output voltage and supplies load current directly during th e conduction phase of the power switch. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging and discharging of the output capacitor. the conservation of charge principle also indicates that, during the boost switch off period, the ou tput capacitor is charged with the inductor ripple current, minus a relatively small output current in boost topology. as a result, the user must select an output capacitor with low esr and adequate input ripple current capability. table 4 shows some recommenda tions of output capacitors. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at 0v. compensation the boost converter of ISL98604 can be compensated by a rc network connected from the comp pin to ground. the resistance sets the high -frequency integrator gain for fast transient response and the capacitance sets the integrator zero to ensure loop stability. on the demo board 5.6k and 15nf rc network is used. stability can be examined by repeatedly changing the load between 100ma and a max level that is likely to be used in the application. the a vdd voltage should be examined with an oscilloscope set to ac and observe the amount of ringing when the load current changes. soft-start the soft-start is provided by an internal current source to charge the external soft-start capacitor. the ISL98604 ramps up the current limit from 0a up to the fu ll value, as the voltage at the ss pin ramps up from 0.8v. hence, the soft-start time is 2.9ms when the soft-start capacitor is 22nf, 6.3ms for 47nf and 13.3ms for 100nf. avdd delay switch ISL98604 integrates a disconnect switch for the avdd boost output to disconnect v in from avdd when the en input is low or when dly2 is not completed. when en is taken high and dly2 timing is finished, the integrated fet is turned on to connect power to the display. the avdd delay switch circuitry constantly monitors both the current flowing through the switch and the voltage at swout. the delay switch has two current limits: a low current limit and a high current limit. if the current flowing through delay switch is higher th an the delay switch low current limit, the ic faults out after 1ms; if the delay switch high current limit is reached, the ic faults out immediately. havdd synchronous buck converter operation havdd synchronous buck converter is a step down converter with a fixed switching freq uency (750khz) supplying voltage bias for gamma buffer in the lcd system. the ISL98604 integrates two mosfets to reduce external component count, save cost, and improve efficiency. in continuous current mode, the relationship between input voltage and output voltage is as shown in equation 7: where d is the duty cycle of the upper switching mosfet. because d is always less than 1, the output voltage of the havdd buck converter is lower than the input voltage. the peak current limit of havdd buck converter is set to 0.9a, which restricts the maximum output current based on equation 8: where i p-p is the ripple current in the buck inductor as shown in equation 9: table 2. boost inductor recommendation inductance dcr (m ) dimensions (mm) vendor part number 4.7h/ 3.4a peak 31 7.3x6.8x3.2 tdk rlf7030t-4r7m3r4 4.7h/ 4.5a peak 44.1 4.0x4.0x3.1 coilcraft xal4030-472meb 4.3h/ 6.4a peak 11.2 12.9x12.9x4 sumida cdep12d38np-4r3m table 3. boost converter rectifier diode recommendation diode v r /i avg rating package vendor ss34 40v/3a do-214 fairchild pmeg3030 30v/3a sod128 nxp table 4. boost output capacitor recommendation capacitor size vendor part number 10f/50v 1206 tdk c3216x5r1h106k 22f/25v 1210 murata grm32er71e226ke15l v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- + = (eq. 6) hvdd v in ----------------- - d = (eq. 7) i havddmax 0.9 i p-p 2 --------------- ? = (eq. 8) i p-p havdd lf s ? ---------------------- 1d ? () ? = (eq. 9)
ISL98604 17 fn7687.0 december 17, 2012 where l is the buck inductance, f s is the switching frequency of hadd buck inductor (750khz). ISL98604 uses internal feedback resistor divider to divide the output havdd voltage down to the nominal reference voltage. the havdd voltage is programmable through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. input capacitor selection of input capacitance is important for input voltage ripple. a ceramic capacitor should be used because of its small esr. another important criteria when selecting input capacitor is that it should be able to support the maximum ac rms current which occurs at d = 0.5 and maximum output current. where i havdd is the output current of the buck converter. table 5 shows recommendations for input capacitors. havdd buck inductor the inductance is selected to meet the output voltage ripple requirements and minimize the co nverter?s response time to the load transient. increasing the inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to load transients. taking all the factors into consideration, a 3.3h to 10h inductor range is recommended for the havdd buck converter. besides the inductance, the dc resistance and the saturation current are also factors that need to be considered when choosing a buck inductor. low dc resistance can help maintain high efficiency. saturation current rating should be higher than the peak inductor current in the application. table 5 shows some recommendations for the havdd buck inductor. output capacitor the output ripple and transient response typically drives the selection of an output capacitor. a 10f or a 22f ceramic capacitor is recommended (see table 7). vio buck converter operation vio buck converter is an asynchronous step down converter with a fixed switching freq uency (750khz) supplying power to the logic circuit of the lcd system. in continuous current mode, the relationship between input voltage and output voltage, is as shown in equation 11. where d is the duty cycle of the switching mosfet. the peak current limit of vio buck converter is set to 2a, which restricts the maximum output current based on equation 12: where i p-p is the ripple current in the buck inductor as shown in equation 13: where l is the buck inductance, f s is the switching frequency of vio buck inductor. ISL98604 uses internal feedback resistor divider to divide the output vio voltage down to the nominal reference voltage. the vio voltage is programmable through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. input capacitor selection of input capacitance is important for input voltage ripple. a ceramic capacitor should be used because of its small esr. another important criteria when sele cting input capacitor is that it should be able to support the maximum ac rms current, which occurs at d = 0.5 and maximum output current. where i vio is the output current of the vio buck converter. table 8 shows recommendations for input capacitors. vio buck inductor the inductance is selected to meet the output voltage ripple requirements and minimize the co nverter?s response time to the table 5. havdd buck converter input capacitor recommendation capacitor size vendor part number 10f/25v 1206 tdk c3216x7r1e106k 22f/25v 1206 murata grm31cr61e226ke15l table 6. havdd buck inductor recommendation inductance dcr (m ) dimensions (mm) vendor part number 6.8h/ 3.6a peak 74.1 4.0x4.0x3.1 coilcraft xal4030- 682meb 6.8h/ 2.8a peak 45 7.3x6.8x3.2 tdk rlf7030t- 6r8m2r8 i acrms d1d ? () ? i havdd ? = (eq. 10) table 7. havdd buck output capacitor recommendation capacitor size vendor part number 22f/16v 0805 tdk c2012x5r1c226k 10f/25v 0805 tdk c2012x5r1e106m table 8. vio buck converter input capacitor recommendation capacitor size vendor part number 10f/25v 1206 tdk c3216x7r1e106k 22f/25v 1206 murata grm31cr61e226ke15l vio v in ---------- - d = (eq. 11) i viomax 2 i p-p 2 --------------- ? = (eq. 12) i p-p vio lf s ? ----------- - 1d ? () ? = (eq. 13) i acrms d1d ? () ? i vio ? = (eq. 14)
ISL98604 18 fn7687.0 december 17, 2012 load transient. increasing the inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to load transients. taking all the factors into consideration, a 3.3h to 10h inductor range is recommended for the vio buck converter. besides the inductance, the dc resistance and the saturation current are also factors that need to be considered when choosing a buck inductor. low dc resistance can help maintain high efficiency. saturation current rating should be higher than the peak inductor current in the application. table 9 shows some recommendations for the vio buck inductor. vio buck diode a schottky diode is recommended for its fast recovery time and low forward voltage. the reverse voltage rating should be higher than the maximum input voltage. the peak current rating should be higher than the current li mit of the vio switch, and the average current rating should be higher than the value given by equation 15. where i vio is the output current of the vio buck converter. table 10 shows diode recommendations.. output capacitor the output ripple and transient response typically drives the selection of output capacitor. 10f or 22f ceramic capacitors (table 11) are recommended. . vcore buck converter operation vcore buck converter is a synchronous step-down converter with a fixed switching frequency (1.5mhz) to generate voltage and supply current to the core circuit of the lcd system. in continuous current mode, the relationship be tween input voltage and output voltage is as shown in equation 16. where d is the duty cycle of the upper mosfet and v in of the vcore buck converter is the output voltage of the vio buck converter. the peak current limit of the vcore buck converter is set to 1a, which restricts the maximum output current based on equation 17: where i p-p is the ripple current in th e buck inductor, as shown in equation 18: where l is the buck inductance and f s is the switching frequency of the vcore buck inductor. the ISL98604 uses internal feedback resistor divider to divide the output vcore voltage down to th e nominal reference voltage. the vcore voltage is programmable through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. input capacitor the input of the vcore buck conver ter is internally connected to the output of vio buck converter. therefore, the output capacitors of the vio buck converter also plays the role of input capacitor of the vcore buck converter. please refer to the ?output capacitor? section of the ?vio buck converter? on page 17 for selection of input capacitors for the vcore buck converter. vcore buck inductor the inductance is selected to meet the output voltage ripple requirements and minimize the co nverter?s response time to the load transient. increasing th e inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to load transients. besides the inductance, the dc resistance and the saturation current are also factors that need to be considered when choosing a buck inductor. low dc resistance can help maintain high efficiency. saturation current rating should be higher than the peak inductor current in the application. taking all the factors into consideration, 2.2h inductors as shown in table 12 are recommended for the vcore buck inductor. table 9. vio buck inductor recommendation inductance dcr (m ) dimensions (mm) vendor part number 6.8h/ 3.6a peak 74.1 4.0x4.0x3.1 coilcraft xal4030- 682meb 6.8h/ 2.8a peak 45 7.3x6.8x3.2 tdk rlf7030t- 6r8m2r8 table 10. vio buck diode recommendation diode v r /i avg rating package vendor pmeg2020ej 20v/2a sod323f nxp semiconductors ss22 20v/2a smb fairchild semiconductor table 11. vio buck output capacitor recommendation capacitor size vendor part number 10f/10v 0805 tdk c2012x7r1a106k 10f/10v 0805 murata grm21br71a106ke51l 22f/10v 0805 tdk c2012x5r1a226m i avg 1d ? () *i vio = (eq. 15) table 12. vcore buck inductor recommendation inductance dcr (m ) dimensions (mm) vendor part number 2.2h/ 1.26a peak 55 3.0x2.5x1.2 tdk vlf302512m t-2r2m 2.2h/ 5.6a peak 35.2 4.0x4.0x2.1 coilcraft xal4020- 222me vcore v in ---------------------- - d = (eq. 16) i vcoremax 1 i p-p 2 --------------- ? = (eq. 17) i p-p vcore lf s ? ---------------------- - 1d ? () ? = (eq. 18)
ISL98604 19 fn7687.0 december 17, 2012 output capacitor the output ripple and transient response typically drives the selection of output capacitor. 10f or 22f ceramic capacitors (table 13) are recommended. v on linear-regulator controller the ISL98604 includes two independ ent linear-regulator controllers for positive output voltage (v on ) and negative voltage (v off ). the v on and v off linear-regulator controller subcircuit is shown in the ?typical application circuit? on page 2. the v on power supply is used to power the positive supply of the row driver in the lcd panel. it consis ts of an external charge pump powered from the switching node (lx) of the boost converter, followed by a low dropout linear regulator (ldo_on). the ldo_on regulator uses an external pnp transistor as the pass element. the onboard ldo controller is a wide band (>10mhz) transconductance amplifier capable of 5ma output curren t, which is sufficient for up to 50ma or more output current under the low dropout condition (forced beta of 10). typical v on voltage supported by ISL98604 is programmable from +19v to +34v through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. v off linear-regulator cont roller and charge pump the v off power supply is used to power the negative supply of the row driver in the lcd panel. it consists of an external diode-capacitor charge pump powered from the switching node of the vio buck converter, followed by a low dropout linear regulator (ldo_off). the ldo_off regulator uses an external npn transistor as the pass element. the onboard ldo controller is a wide band (>10mhz) transconductance amplifier capable of 5ma output current, which is sufficient for up to 50ma or more output current under the low dropout condition (forced beta of 10). typical v off voltage supported by ISL98604 is programmable from -8.1v to -1.8v through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. calculation of the linear regulator base-emitter resistors for the pass transistor of the linear regulator, dc current gain (hfe) and unity gain frequency (f t ) are usually specified in the datasheet. the pass transistor adds a pole to the loop transfer function at fp = f t /hfe. therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency, low gain switching transistor. further improvement can be obtained by adding a base-emitter resistor r be , which increases the pole frequency to: fp = ft * (1 + hfe * re/r be )/hfe, where re = kt/qic. therefore, choose the lowest value r be in the design as long as there is still enough base current (i b ) to support the maximum output current (i c ). for example, the v on linear regulator. if a fairchild mmbt3906 pnp transistor is used as the external pass transistor (q7 in the application diagram), then for a maximum v on operating requirement of 50ma, the data sheet indicates hfe_min = 60. the base-emitter saturation voltage is: vbe_max = 0.7v. for the ISL98604, the minimum drive current is: i_drvp_min = 3ma. the minimum base-emitter resistor, r bp , can now be calculated as equation 19: this is the minimum value that can be used so, we now choose a convenient value greater than this minimum value (e.g., 400w). larger values may be used to reduce quiescent current, however, regulation may be adversely affected by supply noise if r bp is made too high in value. v on /v off charge pump single or multiple stages of charge pumps are needed to generate output voltage higher than v boost and negative voltage. the charge pumps can be driven by switching node of the boost converter and vio buck converter, as shown in ?typical application circuit? on page 2. the number of the charge pump stages can be calculated using equations 20 and 21. where n is the number of the charge pump stages, v d is the forward voltage drop of one scho ttky diode used in the charge pumps. v d is varied with forward current and ambient temperature, so it should be the maximum value in the diode datasheet according to max forward current and lowest temperature in the application condition. once the number of the charge pump stages is determined, the relationship between output vo ltages and the maximum current that the charge pump can deliver can be calculated using equations 22 and 23 as follows: where freq is the switching frequency of the avdd boost, c_fly is the flying capacitance (c64, c 53 in the application diagram). i von and i voff are the loadings of v on and v off . 2.2h/ 5.5a peak 12 7.3x6.8x3.2 tdk rlf7030t- 2r2m5r4 table 13. vio buck output capacitor recommendation capacitor size vendor part number 10f/6.3v 0603 murata grm188r60j106me47d 10f/6.3v 0402 tdk c1005x5r0j106m 22f/6.3v 0603 tdk c1608x5r0j226m table 12. vcore buck inductor recommendation inductance dcr (m ) dimensions (mm) vendor part number rbp_min vbe_max (i_drvp_min - ic/hfe_min = ? = 0.7v () 3ma 50ma () 60 ? ? () ? () 325 = (eq. 19) voff headroom nv in 2nv d voff ? ? = 0 > (eq. 20) von headroom n1 + () avdd n v d von ? ? = 0 > (eq. 21) v off nvin ? 2v d i voff freq c fly () ? ++ () = (eq. 22) v on avdd n + avdd 2 v d ? i von freq c fly () ? ? () = (eq. 23)
ISL98604 20 fn7687.0 december 17, 2012 charge pump output capacitors a ceramic capacitor with low esr is recommended. with ceramic capacitors, the output ripple voltage is dominated by the capacitance value. the capacitance value can be chosen by equation 24: for v on charge pump, f osc is the switching frequency of boost converter; for v off charge pump, f osc is the switching frequency of vio buck converter. v on temperature compensation the ISL98604 can output two levels of v on voltages depending on the temperature. a voltage divider which consists of two resistors (r61 and r62) and a thermistor, as shown in the application diagram connected to tcomp pin is used to determine the v on voltage. figure 21 shows that the v on voltage will be von_lt when the tcomp voltage is above the compensation threshold voltage. if the tcomp voltage is below the compensation threshold voltage, the v on voltage will be von_ht. there is a 20mv hysteresis between the threshold when tcomp voltage rises and the threshold when tcomp voltage falls. r61, r62, and thermistor values are selected to set the v on voltage at desired temperature. von_lt and von_ht are programmable through i 2 c control, which will be described in more detail in section ?i 2 c control? on page 20. i 2 c control the ISL98604 supports all rail outputs with fully programmable i 2 c control. the programmed output values can be stored into eeprom during the operation and read out. the i 2 c protocol defines any device that sends data on to the bus as a transmitter and the receivin g device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, ISL98604 operates as a slave device in all applications. the fall and rise time of sda and scl signal should be in the range listed in table 14. the capacitive load on the i 2 c bus is also specified in table 14. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes duri ng scl high are reserved for indicating start and stop conditions (see figure 22). on power-up, the sda pin is in the input mode. all i 2 c interface operations must be gin with a start condition, which is a high to low transition of sda while scl is high. ISL98604 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 22). all i 2 c interface must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 22). an ack (acknowledge) is a software convention used to indicate a successful data transfer. the transm itting device, either master or slave, releases the sda bus after tr ansmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the ei ght bits of data (see figure 23). write operation to write into a dac register (dr), it requires a start condition from the master, followed by 7-bit device address (010000a 0 ), r/w bit (=0 when writing), a va lid dac register address byte (01h-09h), a data byte, and a stop condition. after each of the three bytes, the ISL98604 responds with an ack. at this time, if the data byte is to be written only to volatile registers, the device enters its standby state. example: writing 21h to register address 01h (havdd) to write data in the dac registers into eeprom, it requires a start condition from the master, followed by 7-bit device address, r/w bit (=0 when writing), control register (cr) address byte (ffh), a data byte of 80h to write data in drs to eeprom and a stop condition. after each of the three bytes, ISL98604 responds with an ack. if the data byte is to be written to eeprom, ISL98604 begins its internal write cycle, which takes 25ms to finish. during the internal eeprom write cycle, the device ignores transitions at the sda and scl pins and the sda output is at high impedance state. when the internal eeprom write cycle is completed, the ISL98604 enters its standby state. example: writing current data in drs into eeprom. read operation to read from the dac register (dr), it first requires to write 00 into the control register (cr) (f fh) to specify that the data is read from dr. then it sends de sired dr address to be read (00h-09h). finally, it reads data from dr, which requires a start condition from master, followed by 7-bit device address (010000a 0 ), r/w bit (= 1 when reading); the second byte c out i out 2v ripple f osc ------------------------------------------------------ (eq. 24) figure 21. v on temperature compensation von_lt von (v) von_ht fbp tcomp vdc r61 r62 ntc temperature when tcomp voltage temperature hysteresis resulted from v tcomp_hyst = 20mv temperature (c) > v tcomp_th = 1.265v table 14. i 2 c interface specification parameter min typ max units sda and scl rise time 1000 ns sda and scl fall time 300 ns i 2 c bus capacitive load 400 pf
ISL98604 21 fn7687.0 december 17, 2012 contains the data read from the specified dr. note that the master will not acknowledge this byte. finally, the last master sends stop condition. example: reading data from dr address 06h (v off ). to read from eeprom first, it first requires to write 01 into the control register (cr) (ffh) to specify that the data is read from eeprom. then it sends the desi red dr address to be read (00h-09h). finally, it reads data from dr, which requires a start condition from master, followed by 7-bit device address (010000a 0 ), r/w bit (=1 when reading); the second byte contains the data read from eeprom. note that the master will not acknowledge this byte. finally, the last master sends stop condition. example: reading data from eeprom address 06h (v off ). sda scl start data data stop stable change data stable figure 22. valid data changes, start, and stop condition sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 23. acknowledge response from receiver
ISL98604 22 fn7687.0 december 17, 2012 register map and register values table 15 shows the address of th e dac registers and their default values. table 16 shows the data format of each register. table 17 shows the parameters corresponding to different register values. table 15. memory map of dac register and eeprom register address data (volatile/ non-volatile) factory default (power-up) avdd 00h 6-bit non-volatile 21h havdd 01h 6-bit non-volatile 20h vio 02h 3-bit non-volatile 03h vcore 03h 4-bit non-volatile 01h von_lt 04h 4-bit non-volatile 09h von_ht 05h 4-bit non-volatile 09h v off 06h 6-bit non-volatile 20h dly1 07h 3-bit non-volatile 01h dly2 08h 3-bit non-volatile 03h dly3 09h 3-bit non-volatile 03h cr ffh volatile 00h table 16. data format of dac register and eeprom avdd (default data: 21h) msb lsb rr100001 havdd (default data: 20h) msb lsb rr100000 vio (default data: 03h) msb lsb rrrrr011 vcore (default data: 01h) msb lsb rrrr0001 von_lt (default data: 09h) msb lsb rrrr1001 von_ht (default data: 09h) msb lsb rrrr1001 v off (default data: 20h) msb lsb rr100000 dly1 (default data: 01h) msb lsb rrrrr001 dly2 (default data: 03h) msb lsb rrrrr011 dly3 (default data: 03h) msb lsb rrrrr011 control register (default data: 00h) msb lsb write eeprom data rrrrrrread eeprom or dr data r: reserved 0h: read dac register data only 01h: ead eeprom data only 80h write all dac register data to eeprom
ISL98604 23 fn7687.0 december 17, 2012 table 17. parameter values corr esponding to register values address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h step hex avdd (v) havdd (v) vio (v) vcore (v) von_lt (v) von_ht (v) voff (v) dly1 (ms) dly2 (ms) dly3 (ms) 0 00h 12.7 6.40 3.0 0.9 19 17 -1.8 0 0 0 1 01h 12.8 6.45 3.1 1.0 20 18 -1.9 10 10 10 2 02h 12.9 6.50 3.2 1.1 21 19 -2.0 20 20 20 3 03h 13.0 6.55 3.3 1.2 22 20 -2.1 30 30 30 4 04h 13.1 6.60 3.4 1.3 23 21 -2.2 40 40 40 5 05h 13.2 6.65 3.5 1.4 24 22 -2.3 50 50 50 6 06h 13.3 6.70 3.6 1.5 25 23 -2.4 60 60 60 7 07h 13.4 6.75 3.7 1.6 26 24 -2.5 70 70 70 8 08h 13.5 6.80 1.7 27 25 -2.6 9 09h 13.6 6.85 1.8 28 26 -2.7 10 0ah 13.7 6.90 1.9 29 27 -2.8 11 0bh 13.8 6.95 2.0 30 28 -2.9 12 0ch 13.9 7.00 2.1 31 29 -3.0 13 0dh 14.0 7.05 2.2 32 30 -3.1 14 0eh 14.1 7.10 2.3 33 31 -3.2 15 0fh 14.2 7.15 2.4 34 32 -3.3 16 10h 14.3 7.20 -3.4 17 11h 14.4 7.25 -3.5 18 12h 14.5 7.30 -3.6 19 13h 14.6 7.35 -3.7 20 14h 14.7 7.40 -3.8 21 15h 14.8 7.45 -3.9 22 16h 14.9 7.50 -4.0 23 17h 15.0 7.55 -4.1 24 18h 15.1 7.60 -4.2 25 19h 15.2 7.65 -4.3 26 1ah 15.3 7.70 -4.4 27 1bh 15.4 7.75 -4.5 28 1ch 15.5 7.80 -4.6 29 1dh 15.6 7.85 -4.7 30 1eh 15.7 7.90 -4.8 31 1fh 15.8 7.95 -4.9 32 20h 15.9 8.00 -5.0 33 21h 16.0 8.05 -5.1 34 22h 16.1 8.10 -5.2 35 23h 16.2 8.15 -5.3 36 24h 16.3 8.20 -5.4 37 25h 16.4 8.25 -5.5
ISL98604 24 fn7687.0 december 17, 2012 protections the ISL98604 integrates overcurrent protection (ocp), overvoltage protection (ovp), and over-tempe rature protection (otp). the protection threshold and the reaction of the chip are listed in table 18. 38 26h 16.5 8.30 -5.6 39 27h 16.6 8.35 -5.7 40 28h 16.7 8.40 -5.8 41 29h 16.8 8.45 -5.9 42 2ah 16.9 8.50 -6.0 43 2bh 17.0 8.55 -6.1 44 2ch 17.1 8.60 -6.2 45 2dh 17.2 8.65 -6.3 46 2eh 17.3 8.70 -6.4 47 2fh 17.4 8.75 -6.5 48 30h 17.5 8.80 -6.6 49 31h 17.6 8.85 -6.7 50 32h 17.7 8.90 -6.8 51 33h 17.8 8.95 -6.9 52 34h 17.9 9.00 -7.0 53 35h 18.0 9.05 -7.1 54 36h 18.1 9.10 -7.2 55 37h 18.2 9.15 -7.3 56 38h 18.3 9.20 -7.4 57 39h 18.4 9.25 -7.5 58 3ah 18.5 9.30 -7.6 59 3bh 18.6 9.35 -7.7 60 3ch 18.7 9.40 -7.8 61 3dh 18.8 9.45 -7.9 62 3eh 18.9 9.50 -8.0 63 3fh 19.0 9.55 -8.1 note: shaded numbers are the factory default at power-up. table 17. parameter values corre sponding to register values (continued) address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h step hex avdd (v) havdd (v) vio (v) vcore (v) von_lt (v) von_ht (v) voff (v) dly1 (ms) dly2 (ms) dly3 (ms)
ISL98604 25 fn7687.0 december 17, 2012 start-up sequence when vin rising exceeds uvlo and en is high, vio and vcore start-up. when vio and vcore reach 90% of the their target values, after a delay time of dly1, pgood rises up and voff soft-starts; when voff reaches 90% of its target value, after a delay time of dly2, avdd and havdd start to rise up. the soft-start time of avdd and havdd depends on the capacitance on the soft-start pin. when avdd and havdd reach 90% of their target values, after a delay time of dly3, v on starts to rise up. dly1, dly2 and dly3 are programmable through i 2 c control, which is described in section ?i 2 c control? on page 20. the detailed start-up sequence is shown in figure 24. layout recommendation pcb layout is critical especially at high switching frequency. the device's performance, including efficiency, output noise, transient response and control lo op stability is dramatically affected by the pcb layout. there are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v dc and v ref bypass capacitors close to the pins. 3. reduce the loop with large ac amplitudes and fast slew rate. 4. the feedback network should sense the output voltage directly from the point of load, and be as far away from the lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at the ISL98604 exposed die plate area. 6. the exposed die plate, on the underside of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissi pation to the surrounding air. 8. minimize feedback input track lengths to avoid switching noise pick-up. a demo board is available to illustrate the proper layout implementation. table 18. ISL98604 protection table category channel trip level (typ) continued fautl time to shutdown chip reaction re-enable mechanism ocp avdd switch peak current higher than 4a na terminate pwm na avdd delay fet ids current higher than 3.1a during operation 1ms shut down whole ic power cycle ids current higher than 6a at start-up and normal operation immediately shut down whole ic power cycle havdd switch peak current higher than 1a or lower switch peak current higher than 0.9a na terminate pwm na vio switch peak current higher than 2a na terminate pwm na vcore switch peak current higher than 1a na terminate pwm na ovp avdd higher than 20.5v on swi pin immediately shut down whole ic power cycle otp junction temp temperature higher than +140c immediately shut down whole ic power cycle
ISL98604 26 fn7687.0 december 17, 2012 vin en vio vcore pgood voff avdd havdd von dly1 dly2 50% 90% dly3 uvlo uvlo 90% 90% 50% vdc vhi vlo notes: 9. vio and vcore start when en is enabled and 90% rising point will occur at the same time. the timing gap between vio and vcore at 90% rising point will be less than 3ms. 10. pgood and v off will be triggered after vio and vcore rise and not before delay time dly1. 11. avdd and havdd start-up after delay time dly2. both are synchronized at 50% rising point. 12. v on will be triggered after avdd and havdd rise and not before delay time dly3. figure 24. ISL98604 start-up sequence
ISL98604 27 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7687.0 december 17, 2012 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL98604 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 17, 2012 fn7687.0 initial release.
ISL98604 28 fn7687.0 december 17, 2012 package outline drawing l40.5x5d 40 lead thin quad flat no-lead plastic package rev 0, 9/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawing: mo-220whhe-1 7. (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 5.00 a b 5.00 5.00 0.40 4x 3.60 36x 0.40 0.20 0.750 0.050 b 0.10 ma c package outline (40x 0.60) 0.00 min 0.2 ref 0.05 max c 0.10 // (40x 0.20) (36x 0.40) b 40x 0.4 0.1 3.65 3.65 6 4

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